The present invention relates to a semiconductor memory device having a memory cell of SRAM (static random access memory) type. More particularly, this invention relates to a semiconductor memory device improved in resistance to soft error.
As the electronic appliances are becoming lighter, thinner and shorter recently, there is also an increasing demand for realizing the functions of these appliances at high speed. In such electronic appliances, the microcomputer is indispensable, and memories of large capacity and high speed are needed in the microcomputer. At the same time, along with the rapid spread and sophistication of personal computers, cache memories of larger capacity are required for realizing processing at higher speed.
As the RAM, generally, the DRAM (dynamic RAM) and SRAM have been used, and especially the SRAM is used where high speed processing is demanded, such as the cache memory. According to its memory cell structure, the SRAM is available in the high resistance load type composed of four transistors and two high resistance elements, and the CMOS type composed of six transistors. In particular, the CMOS type SRAM is high in reliability because the leak current while holding data is very small, and it is in the mainstream at the present.
FIG. 18 is an equivalent circuit diagram of memory cell of a conventional CMOS type SRAM. In FIG. 18, a PMOS transistor P1 (load transistor) and an NMOS transistor N1 (drive transistor) compose a first CMOS inverter, and a PMOS transistor P2 (load transistor) and an NMOS transistor N2 (drive transistor) compose a second CMOS inverter, and input and output terminals are connected complementarily between the first and second CMOS inverters.
That is, a flip-flop circuit is composed of these MOS transistors P1, P2, N1, and N2, in FIG. 18 and the logic state can be written and read at a memory node NA which is the output point of the first CMOS inverter and also the input point of the second CMOS inverter, and a memory node NB which is the output point of the second CMOS inverter and also the input point of the first CMOS inverter.
Further, NMOS transistors N3 and N4 function as access transistors, and the NMOS transistor N3 has its gate connected to a word line WL, the source connected to the memory node NA, and the drain connected to a positive phase bit line BL. The NMOS transistor N4 has its gate connected to the word line WL, the source connected to the memory node NB, and the drain connected to a negative phase bit line BLB.
That is, by selection of word line WL, positive phase bit line BL, and negative phase bit line BLB, the memory value stored in the memory node NA or NB can be read out.
FIG. 19 is a layout diagram of SRAM memory cell corresponding to the equivalent circuit shown in FIG. 18. As shown in FIG. 19, one SRAM memory cell is formed on an N-type well region NW and a P-type well region PW formed on a semiconductor substrate. Further, PMOS transistors P1 and P2 shown in the equivalent circuit are formed in the same N-well region NW, and NMOS transistors N1 to N4 are formed in the same P-well region PW.
The PMOS transistor P1 comprises a source region and a drain region, which are P+ diffusion regions FL100 and FL110 formed by injection of P-type impurity respectively, and a gate region formed between the P+ diffusion regions FL100 and FL110 and a polysilicon wiring layer PL110. Similarly, the PMOS transistor P2 comprises a source region and a drain region, which are P+ diffusion regions FL100 and FL120 formed by injection of P-type impurity respectively, and a gate region formed between the P+ diffusion regions FL100 and FL120 and a polysilicon wiring layer PL120. That is, the PMOS transistors P1 and P2 share the P+ diffusion region FL100 as the source region.
The NMOS transistor N1 comprises a source region and a drain region, which are N+ diffusion regions FL200 and FL210 formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL200 and FL210 and a polysilicon wiring layer PL110. Similarly, the NMOS transistor N2 comprises a source region and a drain region, which are N+ diffusion regions FL200 and FL220 formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL200 and FL220 and a polysilicon wiring layer PL120. That is, the NMOS transistors N1 and N2 share the N+ diffusion region FL200 as the source region.
The NMOS transistor N3 comprises a source region and a drain region, which are N+ diffusion regions FL230 and FL210 formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL230 and FL210 and a polysilicon wiring layer PL140. That is, the NMOS transistors N1 and N3 share the N+ diffusion region FL210 as the source region.
The NMOS transistor N4 comprises a source region and a drain region, which are N+ diffusion regions FL240 and FL220 formed by injection of N-type impurity respectively, and a gate region formed between the N+ diffusion regions FL240 and FL220 and a polysilicon wiring layer PL130. That is, the NMOS transistors N2 and N4 share the N+ diffusion region FL220 as the source region.
The polysilicon wiring layer PL110 functions also as the wiring for connecting between the gate regions of the PMOS transistor P1 and NMOS transistor N1, and the polysilicon wiring layer PL120 also functions as the wiring for connecting between the gate regions of the PMOS transistor P2 and NMOS transistor N2.
At least one or more contact holes are formed each in the P+ diffusion regions FL100, FL110 and FL120, N+ diffusion regions FL200, FL210, FL220, FL230 and FL240, and polysilicon wiring layers PL110, PL120, PL130 and PL140. In order to realize the connection and composition of the equivalent circuit shown in FIG. 18, these contact holes are mutually connected through metal or other upper wiring layers.
Various structures may be considered for upper wiring layers for connecting the contact holes, but for the ease of understanding, in FIG. 19, the connecting wiring of contact holes is indicated schematically by thick solid lines. According to FIG. 19, the P+ diffusion region FL110, N+ diffusion region FL210, and polysilicon wiring layer PL120 are electrically connected through the upper wiring layer to compose the memory node NA, and the P+ diffusion region FL120, N+ diffusion region FL220, and polysilicon wiring layer PL110 are electrically connected through the upper wiring layer to compose the memory node NB.
The P+ diffusion region FL100 is connected to a VDD line, which is a power source line, through the contact hole and upper wiring layer, and the N+ diffusion region FL200 is connected to a GND line, which is a grounding line, through the contact hole and upper wiring layer. The N+ diffusion regions FL230 and FL240 are electrically connected to the positive phase bit line BL and negative phase bit line BLB, respectively, through the contact hole and upper wiring layer. Further, the polysilicon wiring layers PL130 and PL140 are electrically connected to the word line WL through the contact hole and upper wiring layer.
A sectional structure of the conventional SRAM memory cell is explained. FIG. 20 is a sectional view along line A-Axe2x80x2 in the conventional SRAM memory cell layout in FIG. 19. In order to form PMOS transistors P1 and P2, first, the P+ diffusion regions FL100, FL110, and FL120 partitioned by an element separation region 10 are formed on an N-well region NW. After laminating a thin insulating film 21 between the P+ diffusion regions, by laminating polysilicon wiring layers PL110 and PL120 thereon, a gate electrode electrically insulated from the N-well region NW is formed. Meanwhile, the insulating film 21 between the gate electrode and N-well region NW is the gate insulating film of the PMOS transistor.
Consequently, an interlayer film 30 is formed so as to cover the P+ diffusion regions FL100, FL110 and FL120, element separation region 10, and polysilicon wiring layers PL110 and PL120, and contact holes 41 are formed to reach from the top of the interlayer film 30 to the P+ diffusion regions FL100, FL110 and FL120. Finally, a metal wiring 51 of aluminum, tungsten, copper or other metal is formed to cover the contact holes 41, so that the wirings electrically connected to the P+ diffusion regions FL100, FL110 and FL120 are drawn out.
FIG. 21 is a sectional view along line B-Bxe2x80x2 in the conventional SRAM memory cell layout in FIG. 19. In order to form NMOS transistors N1 to N4, first, the N+ diffusion regions FL200, FL210, FL220, FL230 and FL240 are formed on P-well region PW. After laminating a thin insulating film 22 between the N+ diffusion regions, by laminating polysilicon wiring layers PL110, PL120, PL130 and PL140 thereon, a gate electrode electrically insulated from the P-well region PW is formed. Meanwhile, the insulating film 22 between the gate electrode and P-well region PW is the gate insulating film of the NMOS transistor.
Consequently, an interlayer film 30 is formed so as to cover the N+ diffusion regions FL200, FL210, FL220, FL230 and FL240, and polysilicon wiring layers PL110, PL120, PL130 and PL140, and contact holes 42 are formed to reach from the top of the interlayer film 30 to the N+ diffusion regions FL200, FL210, FL220, FL230 and FL240. Finally, a metal wiring 52 of aluminum, tungsten, copper or other metal is formed to cover the contact holes 42, so that the wirings electrically connected to the N+ diffusion regions FL200, FL210, FL220, FL230 and FL240 are drawn out. These NMOS transistors N1 to N4 are formed simultaneously with the PMOS transistors P1 and P2.
The operation of the conventional SRAM memory cell will now be explained. In the equivalent circuit in FIG. 18, for example, supposing the memory node NA to be in logic level xe2x80x9cHxe2x80x9d potential state, the memory node NB is stable in logic level xe2x80x9cLxe2x80x9d potential state. To the contrary, when the memory node NA is in logic level xe2x80x9cLxe2x80x9d potential state, the memory node NB is stable in logic level xe2x80x9cHxe2x80x9d potential state. Thus, the memory cell composed by complementary connection of CMOS inverters has two different stable logic states depending on whether the two memory nodes NA and NB are in xe2x80x9cHxe2x80x9d state or xe2x80x9cLxe2x80x9d state, and the logic state is held as storage data of one bit.
The semiconductor memory device composed of CMOS inverters is very stable and has been free from problem in noise resistance so far. However, as the memory cell per bit becomes smaller and finer in order to realize a memory cell array of large capacity by integrating a multiplicity of memory cells, data held in the memory nodes may be inverted due to electrons generated by alpha-rays released from the package or neutron rays from the space, and soft errors are becoming serious problems.
In particular, soft errors are more likely to occur as the supply voltage declines, and in the recent semiconductor memory devices driven at lower supply voltage, it is becoming an important subject to increase resistance to soft errors.
To avoid soft errors, for example, it has been attempted to increase the capacity of memory node and increase the critical charge amount necessary for inverting the data held in the memory node. According to this method, to invert the stored data, it requires a greater quantity of electrons generated by alpha-rays or the like, so that the probability of occurrence of soft errors may be decreased.
Herein, to increase the capacity of the memory node, it is effective to reduce the thickness of the insulating films 21 and 22, or increase the area in the direction of principal plane thereof. However, from the viewpoint of forming small and thin memory cells, the method of increasing the area of insulating film is not recommended, and hence it is required to form thin insulating films to increase the capacity between the gate and substrate per unit area. However, when thin insulating films are formed, new problems are caused, such as lack of reliability or increase in leak current between the gate and substrate.
That is, since thin insulating films cannot be formed to conform to thin memory cells, the capacity between the gate and substrate is smaller, and the capacity of the memory node of the memory cell cannot be increased, and soft errors are likely to occur.
Further, in order to read and write stored data in the memory cell at high speed, the insulation of the interlayer film 30 is improved, and to decrease the coupling capacity occurring between the impurity diffusion region and polysilicon wiring layer, a material of low permittivity is used as the interlayer film 30. It means that the coupling capacity of the memory nodes NA, NB is decreased, and it is hence difficult to increase the critical charge amount of the memory nodes NA, NB, and soft errors are likely to occur.
It is an object of this intention to provide a semiconductor memory device capable of enhancing the resistance to soft errors by forming at least the gate insulating film of the load transistors for composing the CMOS inverters by using a material of high permittivity so as to increase the capacity between the gate and substrate.
The semiconductor memory device according to one aspect of this invention comprises a first inverter of which output point is a first memory node and input point is a second memory node, the first inverter including a first MOS transistor of a first conductive type; and a second MOS transistor of a second conductive type being different from the first conductive type. The semiconductor memory device also comprises a second inverter of which output point is connected to the second memory node and input point is connected to the first memory node, the second inverter including a third MOS transistor of the first conductive type; and a fourth MOS transistor of the second conductive type. The semiconductor memory device also comprises a fifth MOS transistor of the second conductive type of which drain is connected to the first memory node, source is connected to one of a pair of bit lines, and gate is connected to a word line; and a sixth MOS transistor of the second conductive type of which drain is connected to the second memory node, source is connected to other one of the pair of bit lines, and gate is connected to the word line. Moreover, dielectric constant of a gate insulating film of the first and third MOS transistors is higher than dielectric constant of a gate insulating film of the fifth and sixth MOS transistors.
According to the above aspect, in the load transistor for composing the transistor memory circuit, by forming the gate insulating film of a high permittivity material, the capacity of the memory node connected to the gate of the load transistor is increased.
The semiconductor memory device according to another aspect of this invention comprises plural transistor element regions formed in a semiconductor layer within a same chip, and a wiring region formed by laminating plural metal wiring layers and interlayer films on the top of the transistor element regions, in which the dielectric constant of a specified portion of the interlayer film laminated on the transistor element regions is different from the dielectric constant of the interlayer film in other area than the specified portion.
According to the above aspect, by varying the dielectric constant of the specified portion of the interlayer film on the transistor element regions, the coupling capacity of the interlayer film may be different from the coupling capacity of the portion of the interlayer film other than the specified portion.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.